Verification Engineer


Shanghai, China

Position Type

Full Time

Job Description

  • Setup testbench and develop test cases for embedded FPGA core to ensure good test coverage.
  • Develop UVM testbench for SOC full-chip verification and integrate IP test cases into full-chip UVM environment
  • Build automation test environment to satisfy with CI/CD requirement
  • Work with testing team to deliver quality SOC DFT test vectors and FPGA test patterns

    Minimum Qualifications

    • MS degree with knowledge of digital circuit
    • Good coding skills in Verilog or system Verilog
    • Be familiar with generic SOC interface protocols, such UART, I2C, SPI, APB, AHB etc.
    • Experiences on test coverage analyzing
    • Knowledge of STA and back-annotation simulation

      Deadline to Apply

      Drop us an email, with an attached resume, to
      *We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status