ArkAngel® is eFPGA+Agile Developed methodology, it utilizes different design concepts and approaches to emphasize agile and customized FPGA Fabric, its architecture and resources are optimized for fast iteration and high resource utilization, ArkAngel® provides flexibility and cost-effectiveness for high-volume products.


Towards Automated Prototyping for Versatile FPGAs

• Automate the design, verification and layout of highly versatile FPGA architectures.
• Provide a high-level architecture description language for users to customize their FPGA architectures down to circuit-level details.
• Auto-generate Verilog netlists, with which users can perform verification as well as generate production-ready layouts using modern EDA tools.
• Include a generic Verilog-to-Bitstream generator, as a native EDA toolchain for any FPGAs.
• A showcase the 24-hour layout generation of two FPGA fabrics which are based on Stratix-like architecture built with a commercial 12nm standard-cell library and 40nm custom cells respectively.


An Opensource Framework for Agile Prototyping Customizable FPGAs